1. Field of the Invention
The present invention relates to a clock signal distributing circuit for distributing a clock signal to cells in test device, each of the cells having a clock terminal. The present invention also relates to a method for detecting manufacturing defects in a semiconductor integrated circuit in which many cells are disposed on a chip. The present invention relates particularly to a clock tree construction for distributing a clock signal to a semiconductor integrated circuit, such as a large-scale integrated (LSI) circuit or the like.
2. Description of the Related Art
The number of test patterns used in semiconductor integrated circuits such as LSI circuits, etc., has increased voluminously along with recent increases in the number of memories mounted and recent promotion of large-scale design of the memories themselves. The test time of each memory has also increased, and the cost of the tests has risen.
For example, manufacturing defects of semiconductor integrated circuits such as LSI circuit, etc. are detected by applying a proper signal value to an input pin with a tester, and comparing a signal value appearing at the output pin thereof with an expected result.
The combination of the signal value applied to the input pin and the expected value appearing at the output pin is called a test pattern.
A defect occurring in an LSI circuit due to a manufacturing defect of the LSI circuit is called a failure. Many test patterns are required to test all the failures which are anticipated to occur in an LSI circuit.
Therefore, a test method called a built-in self test (BIST) is frequently used for testing memories containing random access memories (RAM), etc., by generating test patterns in the LSI circuit chip.
In BIST, a pattern generated in a pseudorandom pattern generator is applied to an internal circuit of an LSI circuit, and an output result from the internal circuit is verified and stored by an output verifier. In BIST as described above, the pseudorandom pattern generator is mounted in the LSI circuit, and thus an extremely large number of test data can be generated in a short time.
With respect to the semiconductor integrated circuit, for example, an LSI circuit, the overall LSI circuit is generally operated in synchronism with one clock signal or plural clock signals different in phase. In such a case, a clock signal supplied from an external clock is distributed to the blocks of respective parts in the LSI circuit, whereby read/write operations of a decoder and a memory, various kinds of operations, etc. are performed. However, when the wire length from the clock distributing source to each supply destination is varied, a time lag (clock skew) occurs in the arriving timing of the clock signal.
When clock skew occurs, there is a risk that circuits may malfunction because an erroneous signal is input to each block or undesired beard-like pulses occur at the output of the logic gate. Accordingly, the magnitude of the clock skew becomes a factor for determining the performance (operating speed) of the LSI circuit.
An H-tree type clock distributing circuit has been hitherto used for semiconductor integrated circuits such as LSI circuits, etc. This conventional H-tree type clock distributing circuit is shown a first example of the conventional a LSI circuit in FIG. 6. In FIG. 6, blocks V1 to V16 of plural stages (four stages in FIG. 6) are provided on a chip 60 (in this specification, the chip is defined as each of plural areas into which the LSI circuit is divided). Buffers 61 to 67 are connected to the respective blocks V1 to V16 like a tree by H type clock wires 68 and 69.
More specifically, a clock signal supplied from the external clock to the buffer 61 is successively distributed to the buffers 62, 63, etc. A place which is located on the clock wire between the buffer 63 and each buffer 64 and at the center of the chip 60 is set as an A point. The clock signal supplied to the place A is input to the four buffers 66 through the buffers 64, 65 on the clock wire 68 by the H-type clock wire 68 having the place A at the center thereof. These buffers 66 are respectively located at the four tip positions of the H-type clock wire 68, and the wire lengths from the place A to the four buffers 66 are set to be equal to one another. The group in buffer 66 in each point of H tree is considered to be one buffer with four buffers 66 here.
The output of each buffer 66 is further input to four buffers 67 by the H-type clock wire 69 with the buffer(s) 66 located at the center thereof. These buffers 67 are respectively located at the four tip positions of the H-type clock wire 69, and the wire lengths from the buffer(s) 66 to the four buffers 67 are set to be equal to one another.
By connecting the buffers 64 to 67 through the clock wires 68 and 69 as described above, the clock signal is distributed to the sixteen buffers 67 which are arranged in uniform density within a cell arrangement area of the chip 60. The clock signal distributed to the buffers 67 are supplied from the buffers 67 to the respective blocks V1 to V16. At this time, the wire lengths from the place A to the buffers 67 are equal to one another, and the clock skew at each buffer 67 can be made uniform among the respective buffers 67.
FIG. 7 is a delay chart showing the relationship between the clock and the input data when clock signals having the same phase are supplied to the respective blocks. Here, the clock signal is supplied and the data holding operation is carried out on the basis of the clock signal concerned. As shown in FIG. 6, the clock signal is distributed through the buffers 61 to 67 at the plural stages. As is apparent from FIG. 7, the clock phases 71, 72 of pipe latches (Pipe_Latch) X1, Y1 and the clock phases 73, 74, 75, 76, etc. of the respective blocks V1 to V16 flow in conformity with the data 1.
However, the large-scale design and the high integration have progressed in present LSI circuits, and it is the present situation that the number of order circuits as distribution destinations of the clock signal increases greatly.
Therefore, it has been difficult to create a clock tree having a small clock skew in connection with the increase of the number of the order circuits when the conventional H-tree type clock distributing circuit as shown in FIG. 6 was used.
Therefore, a conventional technique of facilitating the design and production of an LSI circuit as described above, while reducing the clock skew is shown a second example of the conventional LSI circuit in FIG. 8.
In the second example of the conventional LSI circuit, it is important to take whether a register is upstream or downstream of the data flow, as well as the data flow to which a specific register belongs, into consideration during construction of every data flow on LSI 80, for clock trees which are independent of one another to some degree.
This invention relates to an estimating LSI circuit containing a BIST circuit for high-speed test. Accordingly, before an LSI circuit is manufactured, an estimating LSI circuit is created for checking the function/performance of circuits to be mounted in the LSI circuit and for washing out problems.
However, general LSI 80 is an assembly of independent functional blocks, as in the case of the related art as described above, so that it has a plurality of data flow parts as indicated by arrows b of FIG. 8. In the related art, the data flow parts which are different from one another have no relation to one another. Therefore, data are not arranged so as to be collected at one place, but arranged so as to be separated from one another every data flow.
Accordingly, according to the above related art, an independent tree is constructed for every data flow, so that plural types of clock trees are constructed and thus the number of the clock design operations is increased. Therefore, this related art has a problem that it is difficult to construct a proper clock tree used for the logic circuit of an LSI circuit in a short time.
On the other hand, this invention prevents plural data flow parts by adopting BIST. That is, according to this technique, a test pattern flowing in only one direction is input into the estimating LSI.
Accordingly, the design of the clock distributing circuit of this invention makes it easier to construct a clock tree as compared with the related art.
It is important to optimize the clock skew more surely while a clock distributing circuit is designed. Therefore, it is preferable to adjust the insertion and arrangement state of buffers and the number of stages of blocks together with the wiring stage at the lay-out design time.
Furthermore, it is generally desired that a clock tree is created in consideration of the balance of a clock net while viewing a block located at a predetermined position in order to optimize a clock propagation delay time. Here, the clock propagation delay time is a time required for a clock signal from one block to reach each block, and the optimization of the clock propagation delay time is to minimize (make shortest) the delay time.
In FIG. 6 is shown the symmetrical block arrangement of 4×4 blocks of a related art. However, the symmetry of the block arrangement may be actually lost due to restriction of floor plan or the like as in the case of 5×3 blocks, for example. Accordingly, it has been more and more difficult to construct an optimum H-tree type clock wire. As a result, the structure of the H-tree type clock tree has been improper, and it has been difficult to design a clock distributing circuit in which the clock skew and the clock propagation delay time are simultaneously and surely optimized.
The present LSI circuit has plural data flow parts, and it is necessary to construct clock trees which are independent of one another every different data flow. As a result, there are plural different types of the clock trees, and the number of clock design operations increases. Accordingly, it is difficult to construct an optimum clock tree used for a logic circuit of an LSI circuit in a short time.
This invention has been implemented in view of the foregoing problem, and has an object to provide a clock distributing method that can easily construct an optimum clock tree.
Furthermore, this invention has another object to provide a clock distributing method for a clock tree with which an estimating LSI circuit containing a BIST circuit can be tested in a short time.